DC bus stabilization using passive damping network in distributed power system with constant power load

In distributed power system (DPS), the stability performance is always associated with the behaviour of constant power load (CPL). Since DPS large complex system build up from many power electronic converters, the DC bus of the system becomes unstable due to the strenuous action from power converters. When these converters tightly regulated, it behaves as constant power load and exhibit negative incremental input impedance which becomes the main reason in stability degradation of DPS. In this paper, four passive damping network topologies was proposed to reduce the DC bus instability. The best damping performance of the topologies was chosen and analysed using MATLAB/Simulink. The DC bus performances was studied in four cases which are damping behavior due to CPL power level, CPL disconnection, effects of filter and damping capacitor, and effects of filter cut-off frequency. Simulation results obtained shows that the DC bus was successfully stabilized and the resonance damped when passive damper installed. An experimental hardware tests was conducted to verify the proposed damping method and the results were compared with the simulated output waveforms. The analysis results in overshoot, settling time and steady state error of bus voltage shows system improvement with the proposed damper network.


Introduction
Distributed power system (DPS) is a system build up from spatially separated power processing units which connected to electrical loads such as power electronic converter via DC bus [1][2][3][4]. The DPS system are most popular known to be exceptionally suited for power grid integration using renewable energy as power sources and expected to be the key-enabling technology in the future [5]. The main advantage in employing DPS are due to the weight, size, regulatory performance and flexibility of the system [4][5][6]. Due to the wide range of DPS flexibility, it is being used extensively in many fields such as aircraft, hybrid electric vehicles, military naval vessel and telecommunication network [2], [7], [8]. However, there are some unavoidable weakness in DPS. Yet the most critical issue concerned is the stability degradation of the system caused by the interaction of power converters. This could lead to the failure of the system performance.

The causes of DC bus instability in DPS system
When various subsystems interconnected together to one common DC bus bar, the interactions between these subsystems may complicate the whole systems performance. Since each converter in the interconnected system possesses their own internal control function to regulate its output voltage, those converters tend to draw constant power. This causes the power converter produces negative incremental input impedance within their closed loop bandwidth. In [2][3][4][5][6][7][8][9][10][11][12][13] the authors describe that interaction between converters and bus instability causes unequal power distribution among parallel converters which in turn produce enormous stress on the converter module. Moreover, a tightly regulated power converter will exhibit negative incremental impedance which behaves as constant power load (CPL). The existence of CPL is the main reason in the degradation of the systems performance and instability. Constant power load and negative incremental impedance Constant power load is a load that consumes fixed amount of power irrespective the voltage supply received by it [9]. It is usually represented by power electronic converter that attempts to sink constant power from DC bus of the system and causes constant power characteristic arise [14]. This CPL's characteristic is commonly known as negative impedance characteristic or negative incremental impedance. Figure 1 shows the hyperbolic power contour curve of the negative impedance behaviour of constant power load. The curve represents how much current that the load can sink at different voltages up to their maximum power level. The graph behaves such that the current increases as voltage applied to it decrease and vice versa.

Passive Damping Network Topologies
Passive damping is a method used to increase stability of system where damper network consists of resistor, inductor and capacitor configured into certain topology and installed at output filter of the system. A suitable damper should be used for a particular system so that the damping performance and stability of the system can be assured. The Middlebrook stability criterion is a very powerful method in determining stability behaviour of converter when connected to input filter [7]. Therefore, the concept of the instability and causes of resonance output at DC bus need to be studied and analysed carefully in order to come out with the suitable passive damper. Figure 2 shows four different passive damping topologies with its transfer function as proposed in [15].

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By conducting Laplace transform analysis, the transfer function of each topology was obtained. Then, bode plot comparisons of the topologies was performed based on the transfer functions using MATLAB/Simulink software as shown in Figure 3. The value of parameters used for the simulation are L=100 mH, C=1000 µF and R=1 Ω. In the analysis, LC filter circuit was used as reference in determining the damping performance of the different topologies at filter resonance frequency. Based on the bode plot waveforms, at resonant frequency of 100 rad/s, damper topology 1 shows the least peaking which indicates that it has the best damping performance when connected to LC filter circuit. Additionally, the oscillation occur due to instability can also be reduced by installation a resistor in parallel to LC filter as configured in passive damper topology 1. Therefore, damper topology 1 was chosen to be installed in the DPS system with CPL. The damping performance can be further enhanced by installation of a blocking capacitor in series with damping resistor.

Design of DPS Circuit with Passive Damping Network
The chosen damper configuration was modelled as RC series damper having resistor and capacitor arrange in series and plugged in parallel to the DC bus system. The damping resistor serves to damp the instability at filter resonance frequency while the damping capacitor functions to block and prevent the current from entering damping resistor [5] at DC condition. Figure 4 shows the circuit connection of LC filter with passive damping network and CPL which represented by -RL. In the design, the damping capacitor C 2 was assumed to be much larger than filter capacitor C 1 , C2>>C 1 , and that makes impedance of C 2 very small at higher frequencies [2]. Therefore, the total effective resistance of the circuit can be obtained as R eff = −|R|.|R L | |R|− |R L | [2]. From this relationship, it can be seen that when |R L |<|R|, the LC filter will possess a net negative damping which causes DC bus to oscillate [3]. By applying the impedance stability of Middlebrooks criterion, the oscillation can be eliminated and stabilized when damping resistor R is treated to be smaller than R L . This will make the total effective resistance to be positive since the negative impedance characteristic was eliminated [3]. Through some Laplace transform analysis made in the circuit, the output to input voltage transfer function can be obtained as shown in (1) and (2).
Rearranging and equating the denominator in (2), yields (3) Parameter R can be adjusted to set the poles position on s-plane so that it will satisfy the stability characteristic as desired. In order to obtain the passive damping network parameter specification, design analysis was made by factorizing (3) to yields (4): multiplying (4), results in (5) Comparing both (1) and (5), an extra term of arrised. For (1) to be valid, the stability criteria of R L >R was considered and thus creates the term 2 ≫ . This condition results in (6).
At this stage, the parameter of the passive damping network can be obtained provided that damping resistor R acquired first. The damping resistor R must be chosen using (7) such that it satisfies the damping performance of complex poles to the quadratic portion in (5). Damping capacitor can be obtained from (8).

Result and discussion
The circuit was supplied by 115 V DC voltage source. This value is typical DC bus voltage used in an aircraft having loads such as cooling exhaust fan, weather radar, auto throttle and battery charger [16][17]. A step voltage of ±5 V DC is applied at voltage source to step up 8 Ω was used in series with voltage source to represent parasitic element in the circuit. The circuit was then connected to LC filter used previously when comparing damper topologies, having values of L 1 =100 mH and C 1 =1000 µF. The electronic load bank was configured into several CPL power level of 30 W, 60 W and 100 W respectively. The purpose of testing different CPL power level is to investigate how far the passive damper can handle the oscillation suppression of the DPS system. The value of R 2 and C 2 used are 6.7 Ω and 2500 µF, which was obtained using (7) and (8) respectively. These values were chosen based on CPL 100 W power level and by considering the availability of components in experimental hardware set up. The completed designed simulation circuit is shown in Figure 5.
The experimental set up involves the connection of two DC power supplies each supplying main voltage 115 V and step voltage 5 V respectively, oscilloscope, and DC load bank to PCB circuit. The voltage and current were measured using Lecroy WaveSurfer 3024 Series oscilloscope to obtain more enhanced visual of the waveform. For the DC load bank, DC Electronic Load Model M9711 was used to function as CPL since the device can be set to operate in constant power mode. Figure 6 shows the project experimental set up.

Damping Behaviour Due to Different CPL Power Level
For the first test, the performance of the passive damping in eliminating bus oscillation with different CPL power level of 30 W, 60 W and 100 W were examined. The results for both simulation and experiment of DC bus voltage with and without passive damper with CPL power of 60W is shown in Figure 7. The analysis for damping performance was carried out based on voltage/current overshoots, settling time and steady state error responses. Table 1 summarises the comparison of bus voltage behaviour without and with passive damping network for constant DC voltage supply of 115 V.  Based on the waveform in Figure 7, when CPL connected to the system without passive damper, obviously the voltage and current oscillates before settled at steady state value. There were obvious difference in the output waveform where it shows more overshoot and vigorous oscillation as CPL power level increased from 30 W to 100 W. At 100 W, the settling time was 1.06 second which is longer compared to 30 W and 60 W CPL power. On the other hand, the difference between simulation and experiment for steady state error shows rather wide marginal deviation due to the losses occur caused by jumper wires and noises from components of PCB board.
When passive damping network connected to the system, the plots clearly shows the reduction of the DC bus voltage in terms of their overshoot, settling time and steady state error at each CPL power level. The experimental output for 100 W shows that less overshoot difference between system without damper and system with passive damper. This implies that passive damping network performance was not very suitable to be implemented for high power level. However, the settling time and steady state error for all CPL power decreased which indicates the bus stability has been improved.
The circuit was then applied with step of the input voltage of ± 5 V DC. This will cause the voltage at DC bus oscillates at 120 V for positive transience and 115 V for negative transience. The output waveform for DC bus voltage with 60 CPL power level and stepped voltage supply were shown in Figure 8. The simulation and experimental results is summarised as in Tables 2 and 3. When the input voltage is step up to 120 V without passive damper, the output waveform shows overshoot response and oscillates at an average time of 0.70 seconds for simulation and 0.57 seconds for experiment before stable. Consequently, the percentage of overshoot increases with high CPL power level indicating the resonance behaviour or ringing occur at the DC bus. At negative transience voltage back to 115 V, the overshoot and settling time for both simulation and experiment slightly increases compared to positive transience due to the inductive kick when current decreases as result from voltage drop when stepping down the input supply.
With passive damping network introduced to the system, bus voltage at positive transience gives much less overshoot and settling time at an average time of 0.20 seconds. The output waveform produced shows that oscillation has been damped out, giving more stable performance of DC bus system. Subsequently, during step down with passive damping network, the results shows improvement in overshoot, settling time, and steady state error regardless of CPL power level for both simulation and experiment.

Behaviour of DC Bus Voltage When CPL Disconnected From the System
Damping disconnection test was conducted to analyse the bus voltage behaviour when CPL being disconnected from the system. The CPL was first connected to the system and allowed to become stable at steady state value before disconnecting it. Next, the behaviour was compared with presence of passive damper network in the system. Figure 9 shows the DC bus voltage behaviour at 100 W CPL power level during disconnection.
As the CPL power level increases, it can be seen that the voltage oscillates more vigorously and took longer time until it becomes stable. This was presented in Table 4 of 100 W CPL response where the system overshoot at an average of 7.93 percent with 0.49 seconds settling time which are longer compared to response in 30 W and 60 W. However, with passive damping network implemented in the system, the bus voltage waveform shows much better performance when CPL disconnected. The bus voltage shows very small overshoot with faster settling time which indicates the instability has been improved.

Damping Behavior Due to Effects of Damping Capacitor and Filter Capacitor
The passive damper network was connected at all times. The damping capacitor was varied to examine damping performance of the DC bus system. The CPL power level was set to constant value of 60 W throughout the test. Three conditions between the input capacitor filter and the damping capacitor was observed, which C 1 <C 2 , C 1 >C 2 and C 1 =C 2 where C 1 and C 2 represented by filter capacitor and damping capacitor respectively. The capacitors value was presented in Table 5.  Figure 10 shows the simulated DC bus voltage for each capacitor, while Figure 11 gives the experimental output waveform of the system when passive damping network connected at different capacitor relationship. Analysis for overshoot, settling time and steady state error were presented in Table 6.  The DC bus output waveform shows that there was still vigorous oscillation occur even after connecting damper network to the system for capacitor relation C 1 >C 2 . In addition, the voltage oscillates longer with high overshoot for about 0.4 seconds before settled at steady state value. This implies that design of damper network with smaller damping capacitance compared to filter capacitance gives poor damping performance in the system. However, when using larger damping capacitance compare to filter capacitance, the oscillation was suppressed and improved with very low overshoot and faster settling time at 0.15 seconds. This shows that system with C 1 <C 2 gives the best damping performance.

Damping Behaviour Due to Effects of Filter Cut-off Frequency
The purpose of this test was to observe the damping capability of bus voltage when DC load with CPL characteristic connected to filter network with different cut-off frequencies. The filter cut-off frequency was varied to several benchmark values of 50 rad/s, 100 rad/s and 500 rad/s respectively. These values chosen such that frequency of the other two condition is less or more than 100 rad/s of original filter cut-off frequency accordingly. Using the filter cut-off frequency formula = 1 √ , the value of filter inductor and capacitor can be manipulated to give the desired values as presented in Table 7.  Figures 12 and 13 show the results of simulation and experiment respectively. The analysis for overshoot, settling time and steady state error for each cut-off filter frequency level were presented in Table 8. The CPL power level was maintained at 60 W for all frequencies. The results shows significant differences in overshoot for all cut-off frequencies level. Although the differences were quite small, system with 500 rad/s filter presents the smallest overshoot compare to the others. In addition, the settling time was also slightly faster than response of system with 50 rad/s and 100 rad/s, bearing 0.14 seconds upon reaching steady state value. The steady state stays about 1.5 percent at all filter frequencies due to the constant 60 W CPL power used. From this test, it was found that passive damping network with higher filter cut-off frequency able to give better damping performance of the DC bus system.

Conclusion
Passive damping method was proposed in this paper to solve the instability phenomena that occurs in the DC bus. Four common damping topologies were compared and the selected topology was implemented. In designing the passive damping network, stability criteria was always concerned and Middlebrook criterion was used as guideline in the design process. Modelling, analysis and simulation was conducted to choose the best parameters for the circuit configuration and experimental hardware tests was conducted to verify the obtained simulation results. Four tests was conducted to analyse the damper network performances which are damping behaviour due to different CPL power level, CPL disconnection, effects of the combination of capacitor filter and damping capacitor, and also effects of different filter cut-off frequencies.
Analysis of overshoot, settling time and steady state error of the output waveform shows significant improvement in the system with passive damping network. This indicates that the instability occurred in the system has been reduced with the damper installation. Moreover, the damping performance was better with the usage of high damping capacitor which satisfy the

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Middlebrook criterion. It was also found that the damper network able to damp out oscillation better with high cut-off filter frequency. In conclusion, the passive damper have successfully stabilized DC bus in DPS system and the conducted tests has verified the behavior of damping performance.