Application Profiling and Mapping on NoC-based MPSoC Emulation Platform on Reconfigurable Logic

Jia Wei Tang, Yuan Wen Hau, Nasir Shaikh-Husin, Muhammad Nadzir Marsono

Abstract


In network-on-chip (NoC) based multi-processor system-on-chip (MPSoC) development, application profiling is one of the most crucial step during design time to search and explore optimal mapping. Conventional mapping exploration methodologies analyse application-specific graphs by estimating its run-time behaviour using analytical or simulation models. However, the former does not replicate the actual application run-time performance while the latter requires significant amount of time for exploration. To map applications on a specific MPSoC platform, the application behaviour on cycle-accurate emulated platform should be considered for obtaining better mapping quality. This paper proposes an application mapping methodology that utilizes a MPSoC prototyped in Field-Programmable Gate Array (FPGA). Applications are implemented on homogeneous MPSoC cores and their costs are analysed and profiled on the platform in term of execution time, intra-core communication and inter-core communication delays. These metrics are utilized in analytical evaluation of the application mapping. The proposed analytical-based mapping is demonstrated against the exhaustive brute force method. Results show that the proposed method is able to produce quality mappings compared to the ground truth solutions but in shorter evaluation time.

Keywords


Embedded system; application mapping; multi-processor system-on-chips (MPSoCs); through- put constraint;



DOI: http://dx.doi.org/10.12928/telkomnika.v15i3.6513

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