INVESTIGATION OF SHORT CHANNEL EFFECT ON VERTICAL STRUCTURES IN NANOSCALE MOSFET

Munawar A. Riyadi, Ismail Saad, Razali Ismail

Abstract


The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel length (Lch) is demonstrated with the help of numerical tools. The evaluation of short channel effect (SCE) parameters, i.e. threshold voltage roll-off, subthreshold swing (SS), drain induced barrier lowering (DIBL) and leakage current shows the considerable advantages as well as its thread-off in implementing the structure, in particular for nanoscale regime.


Full Text:

PDF

References


A. Khakifirooz and D. A. Antoniadis, "MOSFET Performance Scaling--Part I: Historical Trends," IEEE Transactions on Electron Devices, vol. 55, p. 1391, 2008.

P. M. Zeitzoff, "Trends and challenges in MOSFET scaling," Solid State Technology, vol. 49, pp. 42-44, Feb 2006.

L. R. Harriott, "Limits of lithography," Proceedings of the IEEE, vol. 89, pp. 366-374, 2001.

D. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and Hon-Sum Philip Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proceedings of the IEEE, vol. 89, pp. 259-288, 2001.

Y. T. Hou, M. F. Li, T. Low, and D. L. Kwong, "Metal gate work function engineering on gate leakage of MOSFETs," IEEE Transactions on Electron Devices, vol. 51, pp. 1783-1789, Nov 2004.

H. Wong and H. Iwai, "On the scaling issues and high-k replacement of ultrathin gate dielectrics for nanoscale MOS transistors," Microelectronic Engineering, vol. 83, pp. 1867-1904, 2006.

P. Batude, X. Garros, L. Clavelier, C. Le Royer, J. M. Hartmann, V. Loup, P. Besson, L. Vandroux, Y. Campidelli, S. Deleonibus, and F. Boulanger, "Insights on fundamental mechanisms impacting Ge metal oxide semiconductor capacitors with high-k/metal gate stacks," Journal of Applied Physics, vol. 102, pp. -, Aug 1 2007.

E. Gili, V. D. Kunz, C. H. de Groot, T. Uchino, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, and P. L. F. Hemment, "Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance," Solid State Electronics, vol. 48, pp. 511-519, 2004.

Y. Nishi, "Scaling Limits of Silicon CMOS and Non-Silicon Opportunities," in Future Trends in Microelectronics, S. Luryi, J. Xu, and A. Zaslavsky, Eds.: John Wiley & Sons, Inc., 2007.

K. J. Kuhn, "CMOS scaling beyond 32nm: challenges and opportunities," in Proceedings of the 46th Annual Design Automation Conference, San Francisco, California, 2009.

J. Moers, "Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface," Applied Physics A: Materials Science & Processing, vol. 87, pp. 531-537, 2007.

M. Masahara, Y. Liu, K. Endo, T. Matsukawa, and E. Suzuki, "Vertical Double-Gate MOSFET Device Technology," Electronics and Communications in Japan, vol. 91, pp. 46-51, 2008.

T. Schulz, W. Rosner, L. Risch, A. Korbel, and U. Langmann, "Short-channel vertical sidewall MOSFETs," IEEE Transactions on Electron Devices, vol. 48, pp. 1783-1788, 2001.

I. Saad and R. Ismail, "Scaling of Vertical and Lateral NMOSFET in Nanometer Regime," in Proceedings ISESCO International Workshop and Conference on Nanotechnology, (IWCN 2007), Kuala Lumpur, 2007.

Silvaco, "Product Descriptions - Virtual Wafer Fab, http://www.silvaco.com/products/descriptions/description_vwf.html," Silvaco International, 1995.

C. Lombardi, S. Manzini, A. Saporito, and M. Vanzi, "A physically based mobility model for numerical simulation ofnonplanar devices," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 7, pp. 1164-1171, 1988.

S. A. Schwarz and S. E. Russek, "Semi-empirical equations for electron velocity in silicon: Part I—Bulk," IEEE Transactions on Electron Devices, vol. 30, pp. 1629-1633, 1983.

P. M. Zeitzoff, "2007 International Technology Roadmap: MOSFET scaling challenges," Solid State Technology, vol. 51, pp. 35-37, Feb 2008.




DOI: http://dx.doi.org/10.12928/telkomnika.v7i3.591

Article Metrics

Abstract view : 64 times
PDF - 74 times

Refbacks

  • There are currently no refbacks.


Copyright (c) 2014 Universitas Ahmad Dahlan

TELKOMNIKA Telecommunication, Computing, Electronics and Control
ISSN: 1693-6930, e-ISSN: 2302-9293
Universitas Ahmad Dahlan, 4th Campus, 9th Floor, LPPI Room
Jl. Ringroad Selatan, Kragilan, Tamanan, Banguntapan, Bantul, Yogyakarta, Indonesia 55191
Phone: +62 (274) 563515, 511830, 379418, 371120 ext. 4902, Fax: +62 274 564604

Creative Commons License
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

View TELKOMNIKA Stats