Munawar A. Riyadi, Ismail Saad, Razali Ismail


The recent development of MOSFET demands innovative approach to maintain the scaling into nanoscale dimension. This paper focuses on the physical nature of vertical MOSFET in nanoscale regime. Vertical structure is one of the promising devices in further scaling, with relaxed-lithography feature in the manufacture. The comparison of vertical and lateral MOSFET performance for nanoscale channel length (Lch) is demonstrated with the help of numerical tools. The evaluation of short channel effect (SCE) parameters, i.e. threshold voltage roll-off, subthreshold swing (SS), drain induced barrier lowering (DIBL) and leakage current shows the considerable advantages as well as its thread-off in implementing the structure, in particular for nanoscale regime.

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