Research of 64-bits RISC Dual-Core Microprocessor with High Performance and Low Power Consumption

Gang ZOU, Zhibiao SHAO, Linghao LI

Abstract


A 64-bits RISC Dual-Core microprocessor with high performance and low power consumption is presented in this paper. The processor has a symmetric architecture with two cores. Each of them has three stage pipeline, 64-bit data-path and 64-bit address port. A novel shared register module, redundant Booth3 algorithm and eapfrog Wallace tree architecture are introduced to the microprocessor, and both the performance and power consumption of it has been improved enormously.As the FPGA simulation result indicates, the power consumption is decreased by 14% and the longest data-path is shortened by 25%.

Keywords


Dual-Core, Booth algorithm, Wallace tree



DOI: http://dx.doi.org/10.12928/telkomnika.v16i1.4153

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