Performance improvement of fractional N-PLL synthesizers for digital communication applications

Nour Zaid Naktal, A. Z. Yonis, Khalid Khalil Mohammed

Abstract


Loop filter with two order was designed to improve the performance of the fractional N-phase locked loop (PLL) circuit (reference spurs noise and switching time), decreasing these two factors give good characteristic to fractional N-PLL circuit, the second order and third order loop filters are widely used in frequency synthesizer because they give good stability tolerance and for their simple architecture. They are designed at bandwidth B=125 KHz and its multipoles, at two values of the phase margin (pm)= 35°, 57°. MATLAB program was used to find the lock time, the component values for each element in the loop filter, also the filter impedance T(s), the bode plot of frequency response for close loop (CL) and open loop gain (OL). It is found by comparing the result of the frequency response for the 2nd order loop filter and 3rd order loop filter, that increasing the order of the filter will reduce the spurs noise that destroy the received signal at receiving side.

Keywords


damping factor; PLL; settling time; spurs noise;

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DOI: http://dx.doi.org/10.12928/telkomnika.v19i6.21929

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