A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

D. S. Shylu, P. Sam Paul, D. Jackuline Moni, J. Arolin Monica Helan

Abstract


In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.


Keywords


amplifier; continuous-time (CT) delta-sigma (ΔΣ); loop filter; switch capacitor circuits; voltage-controlled oscillator (VCO)-based ADCs;

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DOI: http://dx.doi.org/10.12928/telkomnika.v18i5.14034

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TELKOMNIKA Telecommunication, Computing, Electronics and Control
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