128 mA CMOS LDO with 108 db PSRR at 2.4 MHz frequency
Astrie Nurasyeila Fifie, Yan Chiew Wong
A low dropout (LDO) voltage regulator with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented in this paper. Large 1µF off-chip load capacitor is used to achieve the high PSRR. However, this decreases the gain and pushes the LDO’s output pole to lower frequency causing the circuit to become unstable. The proposed LDO uses rail-to-rail folded cascode amplifier to compensate the gain and stability problems. 2nd order curvature characteristic is used in bandgap voltage reference circuit that is applied at the input of the amplifier to minimize the TC. The characteristic is achieved by implementing MOSFET transistors operate in weak and strong inversions. The LDO is designed using 0.18µm CMOS technology and achieves a constant 1.8V output voltage for input voltages from 3.2V to 5V and load current up to a 128mA at temperature between -40°C to 125°C. The proposed LDO is targeted for RF application which has stringent requirement on noise rejection over a broad range of frequency.
high PSRR; low dropout (LDO) regulator; low temperature coefficient; power management; rail-to-rail folded cascode amplifier;