A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications

In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for wideband applications. A common-gate input stage is used to improve the input impedance matching and linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure (NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply voltage of 0.8v.


Introduction
Ultra-wideband (UWB) technology has become very popular in recent years due to high demand for wireless high-speed communications.The frequency range of UWB was approved from 3.1-10.6GHz by Federal Communication Committee (FCC) and has commercially been used since 2002 [1][2].Low noise amplifier (LNA) has an important role in receiver as the first active block in the receiving chain.In LNA design, achieve to parameters such as low noise figure (NF), high gain and low input return loss are important respectively to reduce effect of noise from subsequent stages (especially down-conversion mixer) and provide sufficient input matching [3][4].Since second-order harmonic distortion greatly affect the efficiency of direct conversion receivers, those are examined as an important parameter in LNAs.So far, many prototypes have been proposed to achieve convenient features of LNA [5][6][7][8][9][10].In resistive feedback method, it is difficult to simultaneously achieve appropriate gain and noise figure despite achieving appropriate input and stability [5][6].Although distributed amplifiers provide high gain, wide bandwidth and proper input matching, they have a high power consumption and are not suitable for low-power applications [7].
Cascode topology is proposed with current reuse technique to reduce power consumption, but there is the need for high level power supply voltage for proper biasing of its transistors [8][9].A common-gate (CG) topology has been widely used for a wideband LNA because it features wideband impedance matching, superior reverse isolation, stability, and a high linearity compared to a common-source (CS) topology.Although common-gate LNAs feature desirable properties for wideband operation, their high NF under the input-matching condition prevents its extensive use.Additionally, the 3-dB gain bandwidth of CG LNA is rather finite.Using fully differential CG-LNAs is a suitable method to cancel second-order distortion as well as increasing linearity.However, parasitic capacitances increases in these amplifiers due to the large number of transistors which leads to poor performance of LNA in wide bandwidth [10].In this paper, a multi-stage fully differential LNA with negative feedback is proposed to alleviate some common issues and improve the performance of conventional CG-LNAs.The objective of the design is achieving power gain (S 21 ) higher than 15 dB, noise figure (NF) less than 3 dB, input and output return losses (S 11 and S 22 ) less than -10 dB and input-output isolation (S 12 ) less than -30 dB in the frequency band of 5-9 GHz.In addition, the design tries to reduce power 1084 consumption and level of power supply voltage as much as possible.The paper is organized as follows.In Section 2, the proposed LNA is first introduced and a detailed analysis including input impedance, gain, and NF is then explained.Section 3 presents the circuit level simulation results.The results are discussed and compared with recently simulation reported UWB LNAs.Finally, section 4 concludes the paper with some key findings.

Proposed Low Noise Amplifier
The proposed LNA topology with negative feedback along with its simplified singleended model, shown in Figure 1 and Figure 2 respectively.Common-gate (CG) input stage (M 1 and M 2 ) is used for matching of suitable input impedance, bandwidth improvement and high input-outputisolation.However, there is a trade-off between the input matching and noise performance.The noise figure of a conventional CG LNA is inversely proportional to transistor transconductance (g m ), and the input impedance is simplified as 1/g m .Therefore, the transistor transconductance, that defines the input matching condition, limits the LNA performance in terms of noise and gain.To overcome this problem, a common-source (CS) stage (M 3 and M 4 ) is cascaded to increase gain and reduce noise.In addition, a negative feedback has been used to add a degree of freedom in determining the g m of the input matching transistor.A gate of PMOS transistor (M f ) in CS topology is coupled to the output node to obtain a shunt-shunt feedback network.It will be shown below that using the feedback will eliminate the need for high g m1 for input matching which results in reduced power consumption.Moreover, using a PMOS transistor (M f ) in the feedback network eliminates an inductor used at the source of the CG input stage.
In proposed LNA, biasing of all transistors expect for M 7 and M 8 , has been done through the power supply and ground.A proper constant current biasing circuit is used to generate the bias voltages of V B which is not shown in Figure 1  inductor with quality factor (Q s ) of 70 and L 1 , L 2 and L 3 are designed on-chip with Q s =10 at center frequency of f 0 =5.5 GHz.Output buffer stage is also used to achieve appropriate output matching.

Input impedance
A common-gate topology has been widely used for a wideband LNA because it features wideband impedance matching compared to a common-source topology.In conventional differential CG-LNA, the impedance matching is achieved by the size and bias current input transistors (M 1 and M 2 ) to ensure (2/g m1 =50 Ω).Therefore, larger g m1 should be chosen result in high drain current or large channel width (w 1 ).The design can lead to high power consumption and increasing parasitic capacitance of the input transistor.Hence, a shunt-shunt feedback network is employed to reduce the input resistance (R in ) as shown in Figure 3.The feedback theory is used to determine the LNA input impedance as follow: (2) where, β is feedback factor and Rs is source resistance.Z 1 and Z x denote the load impedances at drain of M 1 and M 3 respectively as follow: where, ´ According to (8), the feedback loop provides a degree of freedom so that impedance matching does not set transistor biasing current results in lower g m1 to achieve input matching.The input matching condition for proposed LNA is obtained by Miller approximation as follows: ‖ sL s (9) where, C p1 =C gs1 +C gdf (10) As a result, the input inductor L S can be choose such that the optimal matching frequency falls around the middle of the operation frequency range of 3.5-7.5GHz to ensure wideband input matching condition.

Gain
The conventional CG topology suffer from the low transconductance gain due to its input matching.The CS second stage is intended to increase the gain.Therefore, it is possible to have lower g m 's and consequently a lower power consumption.To derive the bandwidth of the proposed LNA, two dominant parastitic capacitances are considered, as shown in Figure 2.
The parasitic capacitors at the input node v 1 are canceled by L C resonance, and thus, are not considered.C p1 is the parasitic capacitors at the source of M 1 and drain of M f .C p2 is the parasitic effects at the source of M f , M 3 and drain of M 3 by a factor of g m3 r 03 .When using negative feedback, the LNA gain is modified as follows: That A v1 (s) and A v2 (s) are voltage gain of the first floor (including transistor M 1,2 and M f ) and second floor (including transistor M 3,4 ), respectively.Therefore, we have: where,

ISSN: 1693-6930 
A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications (Majid Takbiri) and R 3 is series parasitic resistance of L 3 at resonance.

Noise figure
The noise figure of proposed LNA can be expressed with the following equation:  In which Equation ( 22) is therefore rewritten as follows: F=2 ( where γ is the MOS transistor thermal noise coefficient.As shown in (26), increasing g mf enhances the noise contributed by the feedback network.However, the reduction of g mf will affect the matching of input impedance and gain.Thus, is calculated based on the trade-off between noise figure and input impedance matching.

Simulation Results and Discussion
The proposed circuit has been designed in CMOS 0.18 μm technology and has been simulated using ADS software and model of TSMC Company.The device values of the simulated LNAs and the bias current of transistors are summarized in Table 1.

Table 1. Comparison of Low-Noise Amplifier
Figure 5 demonstrates the effect of changes in the inductances L 1 and L 2 on the proposed LNA power gain.As shown, increasing the inductance at the output of the first stage causes the capacitance of this node to resonate within the considered frequency range and hence increase the power gain.On the other hand, since excessive increase in the inductance interferes with the uniformity of the gain, the inductances were considered as L 1 =7.5 nH and L 2 =6 nH in our design.
Figure 6 shows the effect of changes in the inductance L 3 on the proposed LNA power gain.As shown, since the location of pole in the second stage is determined by the inductance L 3 , its value was selected so as to produce a uniform gain in a broad bandwidth according to the location of the pole in the first stage.
Figure 7 shows the effect of transistor transconductance of the feedback network on the noise figure (NF) of the proposed LNA.As expressed in the NF relation (26), increasing g mf leads to an increase in the output noise of the first stage, which in turn increases the voltage of the output noise.Hence, in the present design, the g mf value was decreased to a minimum in order to decrease NF and matching an appropriate input.Figure 8 shows the effect of changes in the L S on the input return losses of the proposd LNA.As shown by the S 11   Figure 9 shows the s-parameters of the proposed LNA.The proposed LNA includes return losses of the input and output of lower than -9 dB and an input-output isolation of lower than -38 dB at a bandwidth of 3.5-7.5GHz.Given that ultra-wide band signals have a very low spectral power density, squeezing is rarely considered in Ultra-wideband low-noise amplifiers.But due to wide bandwidth of these system and possible interference signals, the third-order input intersection point (IIP 3 ) parameter is the most important parameter related to linearity [11].Two-tone test is done for proposed LNA at the frequency of 5.5 GHz with frequency spacing of 1 MHz.As it can be seen in Figure 12, IIP 3 is equal to -3 dBm.As it can be observed in Table 2, eligibility criteria of proposed LNA is large which shows its proper functionality for use in ultra-wide band receivers.

Conclusion
In this paper, a low noise amplifier has presented using CMOS 0.18 μm technology in ultra-wide band of 3.5-7.5GHz.A multi-stage differential amplifier has been used in proposed LNA for increasing gain and high linearity.Also, a parallel-parallel negative feedback transistor has been used to increase the bandwidth which can provide a good compromise between power gain and bandwidth while achieving a very low noise figure.In addition to having high linearity and good bandwidth in this method, the use of PMOS and NMOS transistors have led to lack of need of the proposed LNA to biasing circuit and reduction of supply voltage level by 0.8 v which will result in low power consumption in about 9 mW.

Figure 1 .Figure 2 .
Figure 1.Proposed LNA structure for simplicity.The capacitors of C i and C o have been considered for DC bias isolation.The inductor of L S have been designed as off-chip TELKOMNIKA ISSN: 1693-6930  A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications (Majid Takbiri) 1085

Figure 3 .
Figure 3. Transistor feedback network with feedback factor of β=g mf of the first floor has the most effect on the noise figure.Thus, noise reduction of the first stage is very important.In proposed LNA, noise of feedback network is also added to the noise of the first stage results in increases in noise figure.On the other hand, noise of the second stage has significant impact on the total noise due to low gain of the first stage.

Figure 5 .Figure 6 .Figure 7 .Figure 8 .
Figure 5.The effect of changes in the inductances L 1 and L 2 on the power gain

Figure 9 .Figure 10
Figure 9.The s-parameters of the proposed LNA

Figure 11 .
Figure 11.Power gain of proposed LNA Figure 12.Third-Order Intersection Point of the proposed LNA

FOM= |S 21
|BW GH z IIP 3,mW (|NF|-1)P mW (27) R´m are the input resistance and open loop transimpedance gain of the input stage with the loading effects of the feedback network, respectively.R 1 and R 2 are respectively series parasitic resistances of L 1 and L 2 at resonance.The LNA can be matched to the source resistance at the resonance frequency can be obtained by:  ISSN: 1693-6930 TELKOMNIKA Vol. 16, No. 3, June 2018: 1083-1091 S leads to elimination of the imaginary part of the input impedance and decreases the return losses at the input.

Table 2 .
Comparison of Low-Noise Amplifier