HARDWARE-RESOURCE SAVING FOR REALIZATION OF SPACE VECTOR PWM BASED ON FPGA USING BUS-CLAMPING TECHNIQUE

The space vector pulse width modulation (SV-PWM) is more suitable and can increase the obtainable DC voltage utilization ratio very much compared to others PWM. Moreover, the modulation can obtain a better voltage total harmonic distortion (THD) factor. But until now, no studies that concern at hardware resources saving to realize SV-PWM based on FPGA. This paper proposes a new technique to realize SV-PWM based on FPGA. In order to get hardware resource saving, a simple technique to judge sectors, to calculate the firing pulses and to generate SV-PWM waveform without calculation of trigonometric function using bus-clamping technique is proposed. The technique has been implemented successfully based on APEX20KE FPGA to drive three phase induction machine 1.5 kW with low ripples in current and voltage, and has been shown that the proposed SVM method required the most minimum hardware resources compared to others research.


INTRODUCTION
The main aim of any modulation technique is to obtain variable output having a maximum fundamental component with minimum harmonics and less switching losses.The Space Vector Pulse Width Modulation (SV-PWM) method is an advanced PWM method and it is possibly the best among all the PWM techniques for variable frequency drive applications.Compared to the Sinusoidal Pulse Width Modulation (SPWM), SV-PWM is more suitable and can increase the obtainable DC voltage utilization ratio very much.Moreover, it can obtain a better voltage total harmonic distortion factor [1][2][3][4][5][6][7][8][9][10][11][12][13].
In most engineering practice, the SV-PWM algorithm is mainly implemented with software based on microcontroller [2, [13][14][15][16][17][18] or digital signal processors (DSP) [19][20][21] are widely adopted.They perform control procedure sequentially by exploiting their mathematically oriented resources.That is the instructions of different procedures are executed one after the other.Thus, the purely software-based technique is not an ideal solution.Differ to software implementation; FPGA performs the entire procedures with concurrent operation by using its reconfigurable hardware.A FPGA is considered as an appropriate solution to boost system performance of a digital controller including an SV-PWM algorithm [2, 6,13,[22][23][24][25][26].
However, the conventional SV-PWM suffers from the drawbacks like computational burden, inferior performance at high modulation indices and high switching losses of the inverter.Hence to reduce the switching losses and to improve the performance in high modulation region, several bus-clamping SV-PWM methods have been proposed [5,21,[27][28][29][30][31].Unfortunately, those are based on the conventional SV-PWM without considering hardware resource saving.This paper present the design and implementation of bus-clamping SV-PWM based on FPGA using new technique.To get hardware resource saving, the simplification of sector identification method, re-arrange the dwelling time to avoid the complex trigonometric calculations, and a novel method to calculate the duration of active vector are proposed.

A NEW APPROACH TO IMPLEMENT 5-SEGMENT BUS-CLAMPING SV-PWM ALGORITHM
This section present symmetrical 5-segment bus-clamping switching sequence with new judge method of sectors, and new SV-PWM generating method based on calculation of the duration of active vectors to avoid complicated computations with trigonometric function.

Proposed SV-PWM switching Pattern (5-segment bus-clamping switching pulses)
There has been reported many bus-clamping SV-PWM pattern [5, 6, 26-28].However, not all those patterns have lower switching losses, simpler algorithm and can be implemented based on FPGA easily.In this paper, a novel symmetric 5-segment bus-clamping SV-PWM design, which it is always a channel staying constant for the entire PWM period is proposed.

Proposed identification of the sector
The methods to judge the sector have been introduced which the reference space voltage vector lies in.Zhi-pu [32] has compared the reference space vector's angle with 0 0 , 60 0 , 120 0 , 180 0 , 240 0 , and 300 0 to obtain the number of the sector that the V ref in.The others, Yu [33], Jiang [23] and Xing [7] have analyzed the relationship between 

V and 
V to determine the sector.They have calculated the projections a V , b V and c V of  V and  V in (a,b,c) plane by using inverse Clark transformation, as follow: Then, based on equation (4) above, they calculate N=sign(Va) + 2*sign(Vb) + 4*sign(Vc).Map N to the actual sector of the output voltage reference by referring to the following relationship: as decompose of the conventional SV-PWM, which will properly counteract the redundant calculations to identify sector location, but it imported the complicated matrix calculations.Hence, through the analyzing of SV-PWM mentioned above, this research has created a simpler method to determine the sectors of voltage vectors based on the comparison between and 0 as shown in Fig. 1.By using the comparison, we can determine the sectors of voltage vectors simpler than [7,23,[32][33][34].

Proposed method to generate SV-PWM switching pulses
The bus-clamping 5-segment bus-clamping SV-PWM has symmetrical switching pulses as in the 7-segment conventional SV-PWM.Therefore, the similar method to generate conventional SV-PWM switching pulses can be adopted in the proposed SV-PWM.To easier implement it based on FPGA, in this research has created a graphical method to generate the SV-PWM switching pulses as illustrated in Fig. 2.
Therefore, the PWM generating for S b and S c channels in sector I can be obtained through comparison between triangle and a T , and between triangle and b a T T  respectively, with S a Channel is set equal to 1.The PWM generating in other sectors can be obtained in a similar way.

FPGA REALIZATION OF A PROPOSED NOVEL SV-PWM
In previous section, the principle of SV-PWM has analyzed.In this section, the implementation of proposed SV-PWM based on FPGA will be presented.The overall of proposed SV-PWM design is shown in Fig. 3.This top module has divided into 5 sub modules, namely ajust_freq, Vbeta_Valfa, find_sector, SVM_generator and deadtime_system module.Fig. 3 Overall of the proposed SV-PWM design

Adjustable Frequency Module
In this module, the source of clock generating is designed to connect L6 pin.In this research, carrier signal frequency is set to 40 kHz and reference signal frequency is set to 50 Hz.To get desired carrier and reference signal frequency, the clock dividing is done.

V α and V β Module
In this research, V α and V β is generated through look up table (LUT) sine and cosine function with memory mapping 360 addresses.The lower, base, and higher numbers of sine and cosine function are 96, 224 and 352 respectively (in 9 unsigned bits).

Sector Identification Module
This module is used to determine sector based on Table 2.The simplification of truth table for comparison results as shown in Table 3 were used to determine number of sector in "csector" sub-module.

Three phase SV-PWM signal generator module
This module can be divided into 4 sub-modules, namely Triangle, Duration_Ta, Duration_TaTb, and SVM pattern sub-module.Triangle sub-module was used to generate triangle carrier signal.In this research, triangle signal generator was sampled 32 times per period and 9 unsigned bits were used to represent, which lower number (equal to base number of reference signal) and higher number each are 224 and 352 respectively.The Duration_Ta and Duration_TaTb sub-module has created based on digital solution of second and fourth column in Table 3 respectively.Then, SVM pattern sub-module was used to generate set of SV-PWM pulses refer to section 2.4 and Fig. 2 above.

SIMULATION AND EXPERIMENT RESULTS
The software to design, compilation, verification and hardware realization based on FPGA APEX20KE in this research has used Quartus II Version 9.0 Web Edition.

Simulation
The parameters has used in this research are listed as follows: V dc /T=1, switching frequency 40 kHz, and reference frequency 50 Hz.The compilation report of proposed SV-PWM generator has shown that the design requires 520 logic elements and 9.216 memory bits.If the requirement of hardware resource to generate proposed SV-PWM is compared to other researches, the method requires is most saving as shown in Fig. 4. It has proved that the proposed SVM method required the most minimum hardware resources.ref [28] 1159 ref [31] 2352 ref [32] 1560 ref [33] 3011

CONCLUSION
This paper has presented the realization of a novel 5-segment bus-clamping SV-PWM based on FPGA at switching frequency 40 kHz, in which the simple judging of sectors, the rearrange calculation method of the firing time and the simple method to generate SV-PWM pulses without complicated computations with trigonometric function have been proposed.The technique has been implemented successfully based on APEX20KE FPGA to drive three phase induction machine 1.5 kW with low ripples in current and voltage, and has been shown that the proposed SVM method required the most minimum hardware resources compared to others research.

Fig. 1 .
Fig. 1.A simpler method to determine the sectors

Fig. 2
Fig.2The proposed method to generate set of SV-PWM switching pulses

Fig. 4
Fig. 4 The comparison of required hardware resources

Table 1 .
Map N to the actual sector of the output voltage reference In[34], Zeliang has adopted the new intermediate vectors  X and  X that he has defined