Optimal Modulation Algorithm for Hybrid Clamped Three-Level Inverter

The principle of a three phase hybrid clamped three-level inverter was presented. Taking sixtyfour switch states into consideration, the operational states of hybrid clamped three-level inverter and different current circuits in different switch states were detailed derived. Optimal modulation algorithm was proposed based on the neutral small vectors by different combination, which can realize the automatic balancing of the neutral-point voltage with few switching cycles and did not need to measure the voltage of the clamped capacitors. The proposed modulation algorithm was also capable of restraining the turn-off over-voltage of the power switching devices effectively. Simulation results were given to verify the feasibility and correctness. Experimental results obtained by DSP-based implementation of the controller on 1 MW prototype show good performance in terms of DC-bus voltages regulation (small neutral point potential function and low DC ripple coefficient) and good sinusoidal current.


Introduction
Nowadays, in order to meet the demands of the high-voltage grades and high-power inverter, an important trend in power electronic has been the replacement of the traditional twolevel inverter by multilevel inverter [1][2][3].With the development of power electronic technology, in [4][5][6][7], multilevel technology has been widely studied in the high-voltage and high-power system, grid-connected wind power system, active power filters, and many other fields.Currently, there is a large variety of such multilevel topologies available [8][9].However, the three phase diode clamped three-level inverter is the most widely used topology.As an effective multilevel implementation, besides the characters of fewer power switching devices, lower input current harmonics, better sinusoidal and high adjustable power factor, diode clamped threelevel inverter also has the advantages of bi-directional energy transfer, lower switching frequency and higher system efficiency, which can satisfy the requirements of higher voltage grades, higher power and lower harmonic pollution trend of inverter [10].The operation and the control of three phase diode clamped three-level inverter have been researched during the last decade and both control and modulation methods have been presented in [11][12].
However, large-scale application of multilevel topology is subjected to the unbalance voltages of capacitors in DC-bus and the turn-off over-voltage for power switching devices [13][14][15], and diode clamped three-level inverter is no exception [16].To solve the above problems, a variety of ideas have been put forward in many research papers [17][18][19].Among these, the topology proposed by Korean scholar Young-Seok Kim in 1993, called the hybrid clamped three-level inverter (HCTLI) has the additional benefits of increased controlled switch states in addition to the general the benefits of diode clamped three-level inverter.Compared to three phased diode clamped three-level inverter, three clamped capacitors are added to three clamped legs.Thus, it can restrain the fluctuations of DC-bus neutral potential, realize the bidirectional current flow and restrain the over-voltages of the power switching devices by charging or discharging clamped capacitors and feasible modulation algorithms.Thereby, due to the opportunities of competitive advantages, HCTLI is generally considered attractive and applied as an inverter for the DC-AC converter.The research of HCTLI has focused so far on control schemes, fewer on the pulse width modulation (PWM) algorithms.Traditionally, in order to restrain the problem of DC-bus capacitor voltages unbalance, these modulation algorithms The purpose of this paper is to analyze the operation of the HCTLI, based on an analytical analysis of current circuit and clamped capacitor states, and to determine if a suitable modulation algorithm can implemented.Concentrated on the three phased HCTLI, a new PWM control algorithm is proposed by different optimal combination of neutral small vectors without the use of three clamped capacitor voltages measured in this paper.It can reduce the fluctuations of DC bus neutral voltage and restrain the over-voltages of the power switching devices.These functionalities of the proposed PWM control algorithm are demonstrated by both simulations and experimental results from a DSP controlled, the 1 MW rated inverter prototype.

Control Principle of HCTLI
HCTLI using insulated gate bipolar transistor (IGBT) switches is presented in Figure 1.The main topology of the HCTLI consists of twelve power switches with anti-parallel diodes, each having voltage stress of U d /2.There are six clamped diodes with three parallel clamped capacitors on phase legs and two DC-bus capacitors (C 1 ,C 2 ) in series on the DC side.The neutral point O of DC-bus is connected directly to three clamped midpoints.
To illustrate operation condition of HCTLI, phase A is set as an example to analyze.It is composed of clamped diodes (D 1a ~D2a ), clamped capacitor C a and four switches (S 1a ~S4a ) with anti-paralleled diodes(D 3a ~D6a ).Bidirectional current paths from load to the DC-bus potentials are achieved via switches (S 1a ~S4a ) and diodes (D 1a ~D6a ).Due to the clamped capacitor (C a ) of HCTLI, switches S 2a and S 3a can not work at the same time.The power switches states of phase A could be represented by S A . S A =1 + indicates the on state of power switches S 1a ,S 2a with S 3a , S 4a off.S A =0 + indicates the on state of power switches S 1a , S 3a with S 2a , S 4a off.S A =0 − indicates the on state of power switches S 2a , S 4a with S 1a , S 3a off.S A =1 − indicates the on state of power switches S 3a , S 4a with S 1a , S 2a off.Thus, the output voltage could be controlled by the switch states described above.

1) S A =1 + state
In S A =1 + , the S 1a , S 2a are turned on and S 3a , S 4a off as shown in Figure 2(a).In steadystate conditions, if the phase current i a is positive, the current flow along with the path: P→S 1a →S 2a →A.On the contrary, the current path will become A→D 4a →D 3a →P.Whatever the direction of ia, the pole A is connected to the positive point P of DC-bus, having the following equations: U AO =U PO =0.5U d .On this occasion, the neutral point of the DC-bus should be remain clamped at one half of the complete DC-bus voltage.The possibility of influencing the neutral point potential is based on the clamped capacitor voltage U Ca .If the voltage U Ca >U PO , the clamped capacitor voltage U Ca remains constant, and the clamped capacitor C a will be discharged in the next switch state.Otherwise the voltage U Ca <U PO , the capacitor C a will be charged along with the path: P→S 1a →C a →D 2a →O, as shown in Figure 2 2) S A =0 + state In Figure 3(a), if the phase current i a is positive in steady-state condition, the current flow along with the path: P→S 1a →C a →D 5a →A.On the contrary, the current path will become A→S 3a →D 2a →C 1 →P.Whatever the direction of i a , the pole A is connected to below point of C a .Three-level inverter has a problem that excessive high voltages may be applied to the power switches, when the floating mid-potential varies from the neutral point potential.In this state, the neutral point potential is changed constantly along with clamped capacitor charged and discharged.If the voltage U Ca >U PO , the positive point P is connected to up point of the C a at this moment.And the C a would be discharged along with the path: A→S 3a →C a →D 3a , while the phase current i a is negative.On the other hand if the voltage U Ca <U PO , the C a would be charged along with the path: P→S 1a →C a →D 2a →O, until the two voltages meet the equation: U Ca =U PO .The path of clamped capacitor charged and discharged is illustrated in Figure 3  3) S A =0 -state In contrast to the state of S A =0 + , the power switches S 1a , S 3a are turned off with S 2a , S 4a on.When the phase current i a is positive in steady-state condition, the current flow along with the path: Q→C 2 →O→D 1a →S 2a →A.On the contrary, the current path will become A→D 4a →C a →S 4a .The conduction path of current is illustrated in Figure 4(a).Similarly, the voltage across the clamped capacitor U Ca is analyzed.As shown in Figure 4(b), if the voltage U Ca >U OQ , the C a would be discharged along with the path: D 6a →C a →S 2a →A.On the other hand, if the voltage U Ca <U OQ , the C a will be charged along with the path: O→D 1a →C a →S 4a →Q, until the voltage of the U Ca has the same value as the voltage U OQ .The output voltage U AO between the inverter pole A and the neutral point O of DC-bus is also zero in S A =0 − .

4) S A =1 -state
The conduction path of current is presented in Figure 5(a), and the switches S 1a , S 2a are turned off and S 3a , S 4a turned on.Under steady-state condition, if the phase current i a is positive, the current flow along with the path: Q→D 6a →D 5a →A.Instead, the current flow path will become A→S 3a →S 4a →Q, when i a is negative.Whatever the direction of i a , the pole A is connected to negative point Q of the DC-bus, having the following equations: U AO =U QO =-0.5U d .In the same way, if the voltage U Ca >U OQ , the U Ca remains constant.And the C a would be discharged in the next switch state.Otherwise, the voltage U Ca <U OQ , as shown in Figure 5  To sum up, the switch states of phase A could be derived, and presented in Table 1.Similarly, this operating principle also applies to phase B and C. Because of four kinds of switch states for each phase, the HCTLI contains 4 3 =64 kinds of switch state combinations.It makes control complicated, but the control accuracy will be improved with switch states increased.

DC-Bus Voltage Balance Analysis
HCTLI topology has been applied in medium and high voltage power applications due to the inherent advantages [20].However, it also has the problem that the neutral point potential floated.It may lead to the issue that the power switches bear excessive high voltage.The HCTLI topology shows that stable neutral point potential determines whether the voltages of two DC-bus capacitors are balanced or not.In practical operation, the neutral point potential would fluctuate, leading to these two voltages of the DC-bus capacitors do not equal completely.Such voltage fluctuations may also result in distortion of the inverter output voltages, harmonic content increased and decrease in the output efficiency.Meanwhile, excessive high voltage that power switch devices withstood would cause the device itself breakdown and make the systematic reliability reduced greatly [16,21].And not only that, the life span of capacitance will also be greatly reduced because of severe capacitor voltages fluctuation, which would greatly damage AC drives.So it is important and significant to balance the DC-bus capacitor voltages.
It is generally known that HCTLI contains 64 kinds of switch states corresponding to 64 voltage space vectors, but among them are some redundant vectors.The neutral point potential is primarily influenced by these redundant vectors generated at the output of the inverter.The distribution of voltage space vectors is presented in Figure 6.It has 64 kinds of voltage space vectors, but there are only 19 kinds of valid and equivalent voltage space vectors after equivalent transformation, including one zero vector V 0 , six small vectors V 1 ∼V 6 , six mid-vectors V 7 ∼V 12 and six large vectors V 13 ∼V 18 .Among of them, the vector V 0 contains 10 kinds of switch states and six switch states for each small vector, while each mid-vector corresponds to two switch states and each large vector corresponds to only one.
Different outputs of the inverter are generated by voltage space vectors based on the combination of 64 switch states in different ways.The analysis of these different output states of HCTLI shows that there are only seven output states associated with the DC-bus capacitors and the load.As Figure 7 shows, the direction of the arrows indicates the direction of loop-current.The switch states that correspond to output states mentioned above are shown respectively: (1) Output state "a": 1 + 0 + 0 + , 0 + 1 + 0 + , 0 + 0 + 1 + ; (2) Output state "b": 1 + 1 + 0 + , 1 + 0 + 1 + , 0 + 1 + 1 + ; (3) Output state "c": 0 (5) Output state "e": There are thirty six combinations for switch states, of which small vectors 1 + 0 + 0 − and 1 − 0 + 0 − all have six kinds of combinations.However, small vectors 1 + 0 − 0 − , 1 + 1 + 0 − , 0 + 1 − 1 − and 1 − 0 + 0 + all have three kinds.Meanwhile, each of mid-vectors 1 + 0 + 1 − and 1 + 0 − 1 − also has six kinds of combinations; (6) Output state "f": Known from the analysis of the above: (i) In "a" and "b" output states, the neutral point potential rises, and the HCTLI outputs positive small vectors.The load is only connected to the capacitor C 1 , which forms a discharge circuit.At this moment, the voltage of C 1 drops and the other rises.(ii) In "c" and "d", the neutral point potential drops, and the HCTLI outputs negative small vectors.The load is only connected to C 2 , and it forms a discharge circuit.In these two states, the voltage of C 2 drops and the other rises.(iii) In "e", the HCTLI outputs neutral small vectors and mid-vectors.The two capacitors C 1 and C 2 are both connected to the load, which constituting two charge-discharge circuits.In theory, the small scale fluctuation of neutral potential can be achieved by some combinations of neutral small vectors and mid-vectors.(iv) In "f" and "g", the neutral point O has no connection and no current to the load.In this case, large vectors are generated.At the same time, the load connects the C 1 and C 2 directly, which have the same value in charge-discharge time and the average current of charge-discharge.In theory, as long as these two capacitors have the same parameters, the neutral point potential would keep constant.Accordingly, the neutral point potential is not affected by the large vectors.
In summary, selecting different vectors to synthesize the reference voltage space vectors will cause different effects on the neutral point potential.

Optimized Modulation Algorithm
Select the appropriate voltage space vectors is the core issue of SVPWM for HCTLI.The hexagonal plane of three-level voltage space vector is divided into six small hexagons of the same shape in conventional modulation algorithm, and then solved by two-level SVPWM in two-level voltage space vector plane [22].However, this conventional modulation algorithm needs to further divide the reference voltage vector regions, because of its intersection area for some vectors.Figure 8(a) shows a new irregular division method adopted in this paper.The vector planes (S = 1, 2, 3, 4, 5, 6) are divided to ensure the reference vector can be assigned to a unique two-level voltage space vector plane.Take the vector plane divided (small hexagonal section S=1, small triangle section N=1) as an example to illustrate and calculate the switch operation time of voltage vectors selected.This triangle demarcates the valid and realizable location for the reference voltage vector.For HCTLI, SVPWM is implemented by synthesizing the reference vector using the three nearest vectors forming a triangle around it.As shown in Figure 8(b), when the reference voltage vector V ref lies to the first region N=1, the V ref can be jointly synthesized by three voltage vectors V 1 , V 7 and V 13 .According to the principle of Volt-second balance, the operation times of V 1 , V 7 and V 13 would be derived at a sampling period through the voltage vectors correction and two-level SVPWM algorithm.
In Figure 8(b), the vector V' ref is corrected by V ref and V 1 as the following function.
Then, the Volt-second balance for the correct reference voltage can be expressed as: HCTLI has 19 kinds of valid and equivalent states of the following type: Switch states S X (x=A,B,C) take values in{1 + , 0 + or 0 − , 1 − } presenting the per unit voltage of the phase with respect to the neutral point.Phase to neutral point voltages are given by: Thus, these voltages could be converted into the α-β coordinate using the following transformation: The corresponding operation times (T 0 , T 1 and T 2 ) of V 1 , V 7 and V 13 are derived by equations (1)~ ( 5) respectively as follows: Where: T S is the sampling period, V refα and V refβ are the components of V ref in α,β axis.
In order to adjust the neutral point potential fluctuations, the conventional modulation algorithm generally detects the voltages of DC-bus capacitors and the clamped capacitors, and then combines the positive and negative small vectors to make it come true.However, It may be equivalent to a hysteretic regulator, which applies only to the case of DC-bus voltage imbalance.The effects of the clamped capacitors and the neutral small vectors are ignored in conventional modulation.Thus, taking fully account of the clamped capacitors charging and discharging effects, a new voltage vector selection method to synthesize the reference vector of SVPWM algorithm is proposed in this paper.Furthermore, choosing different appropriate combinations of neutral small vectors makes voltage vector selection implement.As mentioned above, the reference voltage vector V ref can be jointly synthesized by three voltage vectors V 1 , V 7 and V 13 using the method of seven segment configuration.For SVPWM, the sequence of these three voltage vectors applied during a switching cycle is as follows: In the corresponding six switch states of small vector V 1 , both the positive small vector state {1 + 0 + 0 + } and negative small vector state {0 − 1 − 1 − } have a significant impact on the neutral point potential, and others are neutral small vector states{1 + 0 + 0 − , 1 + 0 − 0 + , 1 + 0 − 0 − , 0 + 1 − 1 − }.Midvectors have two kinds of states{1 + 0 − 1 − , 1 + 0 + 1 − }, while large vector has only one switch state.Therefore, eight kinds of vector states sequences to synthesize reference voltage vector could be obtained as shown in Table 2.
In order to ensure that each switch state change makes only one power switch turn on or off, appropriate switch state should be selected from the neutral small vector and mid-vector to meet the need.For the first of the switch state sequences, the same changes of three-phase switch states are between S 1x and S 4x (x = a, b, c).And the fourth of the switch states, the changes of three-phase power switch states are between S 2x and S 3x (x=a, b, c).Considering the power switch devices S 2a and S 3a can not turn on simultaneously because of the HCTLI topology, the AC load current flows through the primary channel of 1 + and 1 − .In order to improve the quality of AC current waveform and reduce switch losses of power switch devices S 2x and S 3x (x = a, b, c), in the meantime, taking the fluctuations of the clamped capacitor into account, this paper chooses the first sequence to synthesize the reference voltage vector.The first sequence of switch states with corresponding operation times is shown as follow: Similarly, the other vector sequences would be got to synthesize the voltage space vectors in other different sections of the vector plane following the principle proposed.The sequences of corresponding switch states for SVPWM algorithm are shown in Table 3.In the same way, operation times of corresponding vectors in above regions could be obtained by the method proposed.Then, the pulses to control the switch devices on-off could be acquired based on SVPWM principle.The optimized modulation not only can meet the need to synthesize the voltage space vectors as a precondition, but also can balance the neutral point potential automatically.In addition to, it has good features of reducing the switch losses, decreasing switch frequency of S 2x and S 3x .

Simulation and Experiment
A detailed simulation for HCTLI has been built to verify the feasibility of the proposed algorithm based on Matlab/Simulink.The main parameters of simulation are listed in Table 4.
Figure 9 shows the simulation waveforms of HCTLI under steady-state operation.The modulated pole to pole voltage U AB and the output current i a are shown in Figure 9    Similar to the simulation results, the DC-bus voltage is stable and the ratio of the neutral point potential fluctuation is very small.As shown in Figure 10(a), the neutral point potential fluctuation is ±42V, and the DC ripple coefficient is 3.75% measured in the experiment.The waveform display good load current sinusoidal, while controlling the power switch devices turnoff over-voltage effectively.The turn-off over-voltage of the power switch device S 1a is about 200V, when the load current is 305A.Experiment fully illustrated this optimized modulation strategy is able to meet the needs of DC-bus voltage balance, effectively reducing the neutral point potential volatility and turn-off over-voltage of power switch.

Conclusion
The hybrid clamped three-level inverter and the operating conditions corresponding to power switch states were presented in this paper.The basic of the DC-bus capacitor voltages balancing was analyzed.A new SVPWM control algorithm was proposed to ensure balancing the DC-bus capacitor voltages and outputting sinusoidal current are met based on different optimal combination of neutral small vectors without the use of three clamped capacitor voltages measured in this paper.The operated sequences of switch states for this optimal modulation algorithm has been detailed presented.The functionality of the optimal SVPWM algorithm was proven with simulations an experiments of a 1 MW laboratory prototype.The match between the simulation and experimental results validates the the optimal SVPWM algorithm.The hybrid clamped three-level inverter is able to maintain balanced DC-bus capacitor voltages and make lower turn-off over-voltage.Furthermore, it provides better sinusoidal output load current.

Figure 1 .Figure 2 .
Figure 1.Main topology of the hybrid clamped three level inverter (b), until the two voltages meet the equation U Ca =U PO .The neutral point potential of DC-bus is thereby rising in S A =1 + .TELKOMNIKA ISSN: 1693-6930  Optimal Modulation Algorithm for Hybrid Clamped Three-Level Inverter (Yi Liu) 1255 (b).The output voltage U AO is zero in S A =0 + .(a) current flow paths (b) charge/discharge paths of C a (a) current flow paths (b) charge/discharge paths of C a Figure 3. Diagrams of current circuit and clamped capacitor state when S A =0 +

Figure 4 .
Figure 4. Diagrams of current circuit and clamped capacitor state when S A =0

Figure 5 .
Figure 5. Diagrams of current circuit and clamped capacitor state when S A =1 -Table 1. Switch states for phase A of HCTLI

Figure 6 Figure 7 .
Figure 6.Diagram of voltage space vector distribution (e) (f) (g) Figure 7. Current paths under seven output states

Figure 8 .
Figure 8. Diagrams of vector plane division and vector composition

TELKOMNIKA
ISSN: 1693-6930  Optimal Modulation Algorithm for Hybrid Clamped Three-Level Inverter (Yi Liu) 1259 Take the reference voltage V ref shown in Figure 8(b) for example to analyze.

: 1693- 6930 TELKOMNIKA
Vol. 14, No. 4, December 2016 : 1253 -1262 1260 (a) and Figure 9(b) separately, and the total harmonic distortion of the measured current is 3.98%.DCbus capacitors (C 1 , C 2 ) voltages and the neutral point potential fluctuations are shown in Figure 9(c) and Figure 9(d).It is observed that the voltages of two DC-bus capacitors are almost balance.The fluctuation of the neutral point potential is very small, nearly ±5V.

Figure 9 .
Figure 9. Simulation of voltage and current, DC-bus voltages and neutral point voltage

TELKOMNIKAFigure 10 .
Figure 10.Diagrams of neutral point voltage, over-voltage in cutting off and current curves

Table 1 .
Switch states for phase A of HCTLI

Table 2 .
Switch states for phase A

Table 3 .
Switch states sequences for SVPWM

Table 4 .
Main simulation parameters of HCTLI